1. Technical Field
This disclosure relates to sigma delta analog-to-digital converters and, more particularly, to mismatch removal in multibit sigma delta analog-to-digital converters.
2. Discussion of Related Art
The use of multibit quantization in sigma delta analog-to-digital converters (ADCs) is known to impart many advantages, such as high resolution at low oversampling ratios, and better stability and tone behavior. With the proliferation in use of high speed and low power continuous time (CT) modulators, multibit quantization has become important because of its immunity to clock jitter. However, the benefits of large internal quantization come at the cost of designing an error free multibit feedback digital-to-analog converter (DAC), as the non-linearity errors of the DAC are not shaped by the sigma delta loop. Data Weighted Averaging (DWA) techniques have been used for DAC linearization. But the hardware complexity of DWA is exponentially proportional to the number of bits, adds extra delay in the feedback path and increases the overall power consumption of the ADC.
One proposed technique uses a folding or a two-step ADC to reduce power dissipation of the internal quantizer and applies Data Weighted Averaging to the segmented coarse and fine DACs. This technique uses an inter DAC calibration approach entirely in the analog domain and operates a single bit modulator which is inherently linear at high Over Sampling Ratio (OSR) to estimate the average gain of the coarse and fine DACs, and then adjusts the weight of a unit element in the fine DAC so that the ratio of their average gains is equal to the ideal value. This approach involves complexity in control and implementation in the analog circuit and may be less accurate.
Accordingly, there is a need for calibration methods and apparatus for sigma delta analog-to-digital converters.